Chapter 2.8 — Foundry & Fabrication

Every chip in this atlas is designed by one company and built by another, and the building is harder than the designing. Turning a blueprint into working silicon at the leading edge is the most difficult manufacturing humanity does, and one company on one island does the overwhelming majority of it. TSMC makes roughly nine in ten of the world's most advanced logic chips, its 2nm capacity is sold out, and its dominance is simultaneously the foundation of the AI build and its single largest point of failure. This is the chapter where the geopolitics of Chapter 2.12 become physical.

A foundry is a contract chip factory. Nvidia, AMD, Apple, and the hyperscalers design their chips but own no fabs; they hand the designs to a foundry, overwhelmingly TSMC, which manufactures them. The difficulty is almost impossible to overstate. A leading-edge fab costs upward of $20B, runs for years to reach acceptable yield (the fraction of chips on a wafer that actually work), and etches features a few nanometers wide using the extreme-ultraviolet lithography of Chapter 2.9. Progress is measured in process nodes, the "2nm" and "3nm" generations, each denser than the last. The catch, and a theme of this chapter, is that each new node now costs more and delivers less than the one before, which is why value is migrating to the memory and packaging of Chapter 2.7.

One island makes almost all of it

The concentration at the leading edge is extraordinary and worth seeing plainly.

TSMC generated about $40.2B in revenue in the second quarter of 2026, its 2nm node entered volume production and is sold out through the year, and it plans a roughly 70% compound growth in advanced-node capacity through 2028. Its share of the pure-play foundry market dwarfs everyone else's.¹²

Foundry Capacity and Process Leadership

Only a handful of companies can make a modern chip at all, and only three are in the 2nm-class race.

The node race: 2nm, backside power, and the High-NA bet

The leading edge is a three-way contest with diverging strategies. TSMC's N2 node entered volume production in late 2025 and ramps through 2026, its first gate-all-around transistor, with backside power delivery arriving in the A16 node in the second half of 2026; TSMC is deliberately deferring the ultra-expensive High-NA lithography tool, betting that mature machines keep its cost per transistor lower for longer. Intel took the opposite bet: its 18A node reached volume in mid-2025 with backside power (PowerVia), beating TSMC to it, and Intel was the first to put a production High-NA machine to work, genuine technology leads. But Intel Foundry still lacks a TSMC-scale roster of external customers, which is the one thing that would make its comeback real, and its 14A node will be more expensive precisely because of High-NA. Samsung's SF2 process reached above 60% yield and landed a $16.5B Tesla contract as validation, though the AI6 chip reportedly slipped as 2nm production lagged.

The core disagreement, the timing of High-NA lithography, decides the economics of the leading edge for years: Intel is adopting it early to build an advantage, TSMC is deferring it on cost, and ASML (Chapter 2.9) sells the machine to whoever buys. Underneath the contest runs the theme of the whole atlas's hardware layers: as node shrinks deliver less and cost more, value migrates into the packaging and memory of Chapter 2.7, which is why "who wins 2nm" matters somewhat less than it used to.

The Taiwan question, and China's ceiling

This layer is where the two-systems story becomes most consequential. The United States leads chip design and owns none of the leading-edge manufacturing on its own soil; that sits in Taiwan, ninety miles from China. TSMC is diversifying, with an Arizona program now committed to around $265B and 2nm fabs breaking ground there, plus sites in Japan and Germany. But the diversification is slow and back-loaded: Arizona runs a generation behind Taiwan, the advanced packaging and the research and development stay in Taiwan, and roughly a third of TSMC's most-advanced capacity is only targeted for Arizona years out. The uncomfortable conclusion, developed in Chapter 2.12, is that a disruption in the Taiwan Strait would halt the entire AI build at once, and no amount of Arizona construction removes that risk before roughly 2030.

China sits on the other side of the same wall. Its national foundry, SMIC, produces 7nm-class chips using older deep-ultraviolet tools and multi-patterning, the workaround for being denied EUV, but at yields estimated in the 20–30% range that make the economics dependent on state support. SMIC is the manufacturing ceiling on China's entire AI-chip ambition: the Ascend and Cambricon accelerators of Chapter 2.5 can only ship in the volumes SMIC can yield, and pushing below 7nm on purely domestic equipment is judged unlikely before the end of the decade, though a SiCarrier-affiliated domestic immersion tool is in testing at SMIC toward a 28nm domestic flow in 2027. Fabrication and high-bandwidth memory are the two hard limits on Chinese AI, and this is one of them.

Foundry economics: utilization, yield and customer mix

A foundry's moat is expressed through economics as much as transistor density. New fabs absorb capital years before they generate revenue; low initial yields consume wafers without producing saleable dies; and fixed depreciation makes utilization a powerful driver of margins. A node can be technically competitive yet economically weak if it lacks enough anchor customers to fill the fab and spread process-development cost. Conversely, a dense portfolio of customers supplies learning cycles, purchasing scale and cash to finance the next node.

That feedback loop explains the difference between process announcements and a durable foundry franchise. For TSMC, the key questions are pricing, leading-edge utilization, customer concentration and returns on overseas capacity. For Intel and Samsung, the decisive evidence is not a demonstration wafer but repeat external volume from customers that are not affiliated with the foundry owner. Capacity announcements should therefore be read with a lagged-normalization risk: synchronized subsidies can create excess capacity in mature nodes even while the leading edge remains scarce.

Yield, external customers and geographic diversification

The central technical contest is the timing of High-NA lithography, and ASML's order flow is a clean read on who is betting what. Watch TSMC's 2nm and A16 yields and its Arizona timeline; watch whether Intel Foundry lands a marquee external customer at the leading edge, which would introduce real competition for the first time in years; watch Samsung's yield stability and whether its Tesla win holds; and watch SMIC's yields as the real gauge of how fast China can scale domestic AI chips. Above all, the value question runs underneath all of it: as node shrinks deliver less, more of each chip's worth moves into the packaging and memory of Chapter 2.7.

Strategic necessity, geopolitical discount

TSMC (TSM) is presently difficult to substitute at the leading edge and sits upstream of Nvidia, Apple, AMD, and Broadcom. That strategic position supports pricing power, but security attractiveness still depends on valuation and the uncompensated Taiwan tail risk. Intel (INTC) is a high-variance US alternative, with genuine process capability and a government backstop but unproven external foundry demand; Samsung (005930.KS) is the credible second source; GlobalFoundries (GFS) is a US-based mature-node exposure. The equipment makers in Chapter 2.9 diversify foundry-customer risk but remain cyclical. On the Chinese side, SMIC (688981.SH, 0981.HK) is the mandated national champion, while low leading-edge yield makes it primarily a policy and localization thesis rather than a conventional margin thesis.

The one event that breaks everything

The dominant risk here is not competitive but geopolitical: a Taiwan Strait crisis is the single event that would invalidate the entire AI capex thesis in this atlas at once, and it can be sized but not hedged away. Short of that, the TSMC thesis would weaken if Intel Foundry genuinely won external leading-edge customers at scale, introducing real competition for the first time in years, or if Arizona and the other overseas fabs de-risked Taiwan faster than expected. The China thesis changes if SMIC breaks its yield ceiling or acquires a domestic path below 7nm, which would loosen the manufacturing limit on Chinese AI chips and pressure the allied advantage that this layer, like memory, currently represents.

For the platform-level distinction between confirmed fabrication, reported relationships and undisclosed next-generation allocation, see §2.13.

Sources

Linked evidence for this chapter's figures and load-bearing claims: ^{1 2}