Chapter 2.9 — Equipment & EDA

Beneath the foundries sit the companies that sell them their machines and their design software, and these are among the best businesses in the entire chain, because they get paid by every chipmaker regardless of which one wins. Five equipment makers dominate the tools, one of them, ASML, holds an outright monopoly on the single machine without which no advanced chip can be made, and two companies control the software used to design almost every chip on earth. This is also the layer where export controls are wielded most precisely, because denying a country these tools freezes its progress in place.

To build a chip you need two things the foundry itself does not make: the physical machines that etch, coat, and inspect the silicon, known collectively as wafer-fab equipment (WFE), and the software used to design the chip in the first place, electronic design automation (EDA). Both are quiet, unglamorous, and extraordinarily profitable, because they are picks-and-shovels sold to everyone in the gold rush. The WFE market runs around $116B a year and is growing on the back of AI-driven memory and logic demand. It is also the most concentrated set of chokepoints in the supply chain, which is precisely why it has become the sharpest instrument of technology policy.

Five machines, and one monopoly

The equipment market divides cleanly, with each of the five giants owning a step of the process.

The most important of them is ASML. It is the sole maker of extreme-ultraviolet (EUV) lithography machines, the systems that print the finest features on a leading-edge chip, and its monopoly is total: no EUV, no advanced logic or memory. Its next-generation High-NA machine costs roughly $350–400M each, and the first units have gone to Intel, SK Hynix, and Samsung. Applied Materials and Lam Research dominate the deposition and etch steps, Tokyo Electron holds about 91% of the coater-developer niche, and KLA controls process-control and inspection with more than 85% of the optical-inspection market. Because each owns its step, they do not so much compete with one another as ride the same wave of fab construction together.

Semiconductor Equipment and EDA Landscape

The roster spans lithography, the process-step leaders, the design-software duopoly, the advanced-packaging machine makers, and the Chinese localization champions.

The EDA duopoly

The design-software layer is a story of concentration as extreme as the equipment.

Synopsys and Cadence, the two American EDA leaders, together hold well over half the market, with Siemens EDA a distant third, and their software is so embedded in how chips are designed that switching is nearly unthinkable; both are increasingly weaving AI into the design process itself, with tools like Synopsys's DSO.ai and Cadence's Cerebrus. It is a duopoly with the pricing power that implies, and, like the lithography layer, a weapon: when the US briefly required export licenses for chip-design software to China in 2025, Synopsys suspended its guidance and halted China sales overnight, before the rule was rescinded weeks later in a trade truce. China's own EDA champions, Empyrean and Primarius, hold only about a tenth of their home market and lack a full-flow tool suite for the most advanced nodes.

The tools are the sharpest weapon against China

This layer is where the US and its allies hold their most decisive leverage over China, and where they have used it. China has pushed its equipment self-sufficiency to roughly 35%, and its national champions have grown fast: Naura has climbed to about the fifth-largest equipment maker in the world, its revenue heading toward $7B, and AMEC's etch tools approach the cutting edge. But the gap that matters is lithography. China has no domestic EUV; its most advanced homegrown machine, from SMEE, does older deep-ultraviolet work, and while a SiCarrier-affiliated immersion-DUV tool is being tested at SMIC toward a 28nm domestic flow in 2027, integration into a production line at scale is years out. Denying China EUV is what caps SMIC's fabrication ceiling in Chapter 2.8, and denying it the servicing and spares for the tools it already owns is a newer, quieter escalation that the US has pressed the Netherlands and Japan to join. The exposure runs both ways, though: China is a large customer, historically around a fifth of Cadence's revenue and a meaningful slice of ASML's (guided down toward 20% for 2026), so the same controls that constrain China also cost the toolmakers.

The packaging-equipment boom

A newer growth vector inside this layer is the equipment for advanced packaging, driven by the CoWoS bottleneck of Chapter 2.7. As TSMC quadruples its packaging capacity, demand flows to the makers of the bonding and assembly machines: Besi, whose hybrid-bonding tools are central to the next generation and which runs a joint venture with Applied Materials; ASMPT and Kulicke & Soffa; and Applied Materials itself. High-bandwidth memory intensifies this, because a bit of HBM consumes roughly three times the wafer-fab capacity of a bit of ordinary memory, so the AI build drives disproportionate equipment demand at exactly the packaging and memory steps where value is concentrating.

The installed base, qualification cycle and normalization risk

Equipment economics extend beyond the initial tool sale. A qualified process tool generates spare-parts, service, software and upgrade demand over a long installed life, making the installed base a stabilizer when new-fab spending slows. Process control and lithography can be especially sticky because changing a tool alters the process recipe and may force costly requalification. Technical service intensity, installed-base growth and recurring revenue therefore deserve separate attention from annual wafer-fab-equipment shipments.

The same stickiness does not remove cyclicality. Customers can pull equipment forward ahead of an export-control deadline, double-order during a shortage or pause once a fab shell has been equipped. A strong shipment quarter can therefore borrow from the future. The underwriting sequence should be: end-market wafer demand, customer utilization, fab construction, tool orders, revenue recognition and finally service attachment. SEMI's equipment forecast is an industry spending measure, not a promise of identical growth or margins for every vendor.¹

Customer concentration and geographic mix are equally important. China restrictions can remove addressable products while localization spending temporarily raises demand for permitted tools. Memory suppliers' synchronized expansions can create a sharp up-cycle followed by digestion. The most defensible suppliers are those whose process step becomes more intensive at each node, whose installed bases compound, and whose tools remain difficult to replace without yield loss.

Orders that distinguish expansion from pull-forward

The defining technical question is the timing of High-NA lithography, the same debate as in Chapter 2.8, and ASML's order flow is a clean read on who is betting what. Watch China's self-sufficiency percentage and whether it can finally close the lithography gap; watch the export-control and servicing rules for further escalation or relaxation; watch the packaging-equipment makers as CoWoS capacity keeps expanding; and watch the WFE cycle itself, because this layer is cyclical and a downturn would hit all five giants together regardless of the AI narrative.

Tools, software and the cycle

ASML (ASML) is the supply chain's most concentrated lithography chokepoint, with China exposure and the timing of leading-edge capacity as major swing factors. Applied Materials (AMAT), Lam Research (LRCX), KLA (KLAC), and Tokyo Electron (8035.T) diversify across process steps and customers, but remain exposed to wafer-fab-equipment normalization. Synopsys (SNPS) and Cadence (CDNS) form the EDA duopoly and carry software-like recurrence alongside semiconductor-cycle exposure. Besi (BESI) is a more concentrated packaging-equipment expression. Naura (002371.SZ) and AMEC (688012.SH) are Chinese localization beneficiaries, with Entity List exposure and a persistent domestic-lithography ceiling. None of these strategic positions eliminates entry-valuation risk.

The cycle, and the China swing

The equipment thesis is cyclical at its core, so the main risk is a WFE downturn, which would affect all five giants despite the AI narrative. ASML's specific exposure is China: tighter export controls could remove addressable revenue, while relaxation would add to it. A credible Chinese breakthrough in domestic lithography would gradually weaken a central allied point of leverage over advanced Chinese chipmaking. The EDA duopoly would also face a new question if AI-driven design tools lowered the barrier to a credible competitor, although current evidence does not establish such a challenger.

For how these upstream production constraints surface in the four anchor accelerator and AI-factory systems, see §2.13.

Sources

Linked evidence for this chapter's figures and load-bearing claims: ^{2 1 3 4 5 6 7}