Chapter 2.7 — Memory & Packaging

Two of the least visible layers in the stack have quietly become the most valuable and the most constrained. High-bandwidth memory now accounts for more of a top GPU's cost than the logic chip itself, and it is sold out. Advanced packaging, the step that bonds the memory and the compute together, is the single gating bottleneck on how many AI chips the world can build. As the shrinking of transistors delivers less each generation, the value of an accelerator is migrating off the logic die and into the memory and packaging around it. Own the bottleneck, not just the compute.

An AI accelerator is not one chip but an assembly. At its center is the logic die that does the computing, and stacked right beside it is high-bandwidth memory (HBM), several dozen layers of DRAM bonded into towers that feed the processor. The reason this matters is that modern models are limited less by how fast a chip can calculate than by how fast it can be fed data, the "memory wall." More and faster memory, placed as close as physically possible to the compute, is what breaks that wall. Advanced packaging is the manufacturing art of putting all of it, logic and memory, onto one tightly-integrated module; the dominant method, TSMC's CoWoS, is what physically makes a modern GPU possible. Neither layer designs the chip, but without them there is no chip.

The value has moved into the memory

The clearest way to see this layer's importance is in the bill of materials. On Nvidia's A100 a few years ago, HBM was roughly a fifth of the component cost. On the current Blackwell generation it is more than half, and on the coming Rubin generation it is tracking toward nearly two-thirds.¹

That shift is the whole investment thesis for this layer. As Chapter 2.8 explains, shrinking transistors now costs more and delivers less, so the extra performance each GPU generation needs comes increasingly from more memory and better packaging rather than from the logic die alone. Memory is no longer a commodity component bolted on at the end; it is becoming the most expensive and most differentiated part of the chip, and with HBM4 its base layer is being built on a logic process at TSMC, tying the memory makers and the foundry together and opening the door to semi-custom HBM designed for a specific customer's chip.

Memory and Advanced Packaging Ecosystem

The layer runs from the three memory makers through the packaging houses to a set of Japanese materials suppliers that most investors have never heard of but that gate the whole thing.

The three-way memory race

The HBM market is a tight oligopoly of three. SK Hynix is the clear leader, with about 57% of HBM bit shipments, having won the Nvidia relationship early and held it. Samsung is fighting to recover lost ground at around 22%, and Micron, the sole American maker, has climbed to about 21%.²

The coming HBM4 generation is the 2026 event, and it changes the competitive stakes. All three vendors qualified for Nvidia's Rubin platform, with the split expected around 50% SK Hynix, 30% Samsung, and 20% Micron, and because HBM is sold out the pricing power sits with the sellers. HBM4 sells for around $500 per stack, more than $10 per gigabyte against $7–8 for the prior generation. The deeper change is that HBM4's base die moves to a logic process fabricated at TSMC, which both couples the memory makers to the foundry and turns HBM from a commodity into a semi-custom product, potentially eroding the brutal price cyclicality that has always defined memory. The two open questions are whether Samsung's yields recover enough to hold its 30% slot after missing the prior generation's qualification, and whether TSMC's role in the base die hands the foundry leverage over the memory makers. Micron is the most accessible pure-play for a US investor; SK Hynix and Samsung trade in Korea.

The packaging monopoly and its hidden chokepoints

Packaging is even more concentrated than memory, and it hides some of the most extreme single-supplier dependencies in the entire supply chain. TSMC's CoWoS is the gating resource for the whole AI-chip industry, and its capacity, around 70,000–80,000 wafers a month at the end of 2025, is being pushed toward 120,000–130,000 by the end of 2026, with the overflow subcontracted to Amkor and Taiwan's SPIL. Nvidia alone is expected to consume roughly 700,000 CoWoS wafers in 2026. Beneath the package sits the substrate, and here a Japanese duopoly of Ibiden and Shinko holds more than 70% of the high-end, with Ibiden the dominant supplier for Nvidia's top GPUs and spending ¥500B to expand.

The most extreme chokepoint of all is nearly invisible: Ajinomoto, a Japanese company better known for seasoning, makes more than 95% of the insulating film (ABF) that every high-end chip package is built on, and it raised prices about 30% for the second half of 2026. Around it sit other Japanese materials names that gate the layer: Resonac supplies the epoxy molding compounds and Namics the underfills that hold these packages together. The next shift to watch is glass substrates, which promise large speed and power gains over today's organic substrates: SK Absolics (a unit of SKC) is preparing mass production in Georgia with samples to AMD, Intel has begun licensing its glass technology, Samsung targets glass interposers by 2028, and Corning and Japan's AGC supply the glass itself. These are the sort of single-supplier dependencies that do not show up in headlines until they break.

America's memory, Asia's packaging, China's gap

The national map of this layer is distinctive. Memory is a Korean and American strength: SK Hynix and Samsung in Korea, Micron in the US, with Japan and Taiwan supplying the materials and the packaging. China is conspicuously behind. Its DRAM champion, CXMT, is scaling fast and just completed the largest chip IPO of 2026, but it trails badly in HBM specifically, and Huawei's push to build its own HBM for the Ascend accelerators of Chapter 2.5 is an attempt to close a gap that is currently one of the two hardest constraints on China's entire AI-chip effort. The other, leading-edge fabrication, is Chapter 2.8.

This is the layer, more than almost any other, where export controls bite China hardest. High-bandwidth memory has been a specific target of restrictions, because it is the component China can least easily substitute, and its scarcity is why Chinese accelerators lean on stockpiled or domestically-produced memory that lags the frontier. Packaging is similar: the CoWoS capacity that makes Western AI chips is in Taiwan, and China is building domestic advanced-packaging capacity but from well behind. For an investor the read is that memory and packaging are where the American and allied position is strongest and the Chinese position weakest, the mirror image of the materials layer in Chapter 2.10.

Qualification, capacity and the memory cycle

Three things. The first is the HBM4 ramp and whether it stays sold out, which would preserve the pricing power that makes memory such an attractive part of the chain right now; the risk is that memory is historically cyclical, and every past boom has ended in oversupply and a price crash. The second is whether Samsung's yields recover enough to hold its 30% HBM4 share or whether SK Hynix extends its lead. The third is packaging capacity: whether TSMC's CoWoS expansion actually relieves the bottleneck or whether each new GPU generation, consuming ever more package area, keeps demand ahead of supply. And a slower structural question runs underneath: whether glass substrates begin to displace organic ones and reshuffle the substrate hierarchy later in the decade.

Owning the rising share of the chip

Micron (MU) is the most accessible US-listed pure-play in the memory group, while SK Hynix (000660.KS) is the HBM leader and Samsung (005930.KS) a turnaround case for investors with Korean-market access. All remain exposed to memory-cycle supply response. The packaging constraint accrues partly to TSMC (TSM), with Amkor (AMKR) and ASE (ASX) as outsourced-assembly alternatives and Besi (BESI) exposed to hybrid bonding. Ibiden and Ajinomoto are difficult-to-replace substrate inputs but may be less accessible; SK Absolics and Corning (GLW) are longer-dated glass-substrate options. Memory and packaging capture a rising share of system value, but capacity additions, qualification and entry valuation determine whether that trend produces excess returns.

The cycle that always turns

The biggest risk to this layer is its own history: memory is cyclical, and the current sold-out, high-price condition has always, eventually, given way to oversupply and a brutal price decline. A wave of new HBM capacity arriving faster than demand, or any stumble in AI-chip build rates, would hit the memory makers hard and fast, and the same efficiency shock that threatens the compute layer would flow through here too. On the packaging side, the thesis weakens if CoWoS capacity finally overshoots demand, turning a scarce, high-margin service into a commodity. And a genuine Chinese breakthrough in domestic HBM, which is not close today, would over time erode the allied advantage that makes this layer such a clean expression of the Western position in AI.

For the package-to-system mapping of HBM3E, HBM4, host memory and disclosed supplier relationships, see §2.13.

Sources

Linked evidence for this chapter's figures and load-bearing claims: ^{2 1}