Chapter 2.5 — AI Chips & Accelerators

“Who sells the most AI chips?” has three incompatible answers. Units favor custom silicon, revenue favors merchant accelerators, and delivered compute depends on the entire system. The investor should therefore follow margin and system control, not a single market-share headline.

An AI accelerator is a chip built to do the one kind of arithmetic that neural networks need, the multiplication of large matrices, thousands of times in parallel. A general-purpose CPU does a few things in sequence very fast; an accelerator does one thing across thousands of cores at once, which is exactly what training and running a model requires. The performance that matters is measured in floating-point operations per second (FLOPS), increasingly at low precision (the FP4 and FP8 formats that trade a little accuracy for a lot of throughput), and in how much high-bandwidth memory sits next to the compute. The most important shift in this layer is that the unit of sale is no longer the chip. Nvidia now sells the rack, an integrated "AI factory" of dozens of GPUs, CPUs, switches, and liquid cooling, and prices it accordingly.

The distinction between a specification and useful output is crucial. A chip can advertise more operations per second and still deliver less economic value if data cannot reach it, software cannot use it efficiently, or the surrounding cluster is unreliable. A customer buying training capacity is not purchasing a number on a data sheet; it is purchasing the time required to reach a model result. A customer buying inference is purchasing completed tokens or tasks at an acceptable latency and cost.

That creates three different denominators. Chip performance asks what one accelerator can do under a defined test. System performance asks what a complete rack or cluster can do after memory, networking, cooling, and software losses. Economic performance asks how much useful work the customer receives per dollar and per watt over the system’s operating life. The first denominator is easiest to market. The third is the one that determines orders.

This is also why a faster accelerator can expand the revenue of suppliers far beyond the logic die. More memory may be required to keep the chip fed. More switch and optical content may be needed to connect a larger cluster. Higher rack density may require new power shelves and liquid cooling. The accelerator chapter is therefore the center of the stack, not the whole stack. §2.13 turns that distinction into an explicit package-to-system-to-facility bill of materials.

A chip is now one part of a jointly delivered system

The roster of accelerators divides into three groups: the merchant GPUs anyone can buy, the custom ASICs the hyperscalers design for themselves, and the Chinese chips built behind the export-control wall.

The supplier groups differ by business model. Nvidia and AMD sell merchant accelerators. Broadcom and Marvell design custom chips for other companies. Google, Amazon, Microsoft, Meta, and OpenAI are developing internal silicon. Huawei and Cambricon lead China's domestic group, followed by Biren, MetaX, Moore Threads, and Hygon.

The three groups solve different purchasing problems. Merchant GPUs offer flexibility: a customer can run many models, use a broad software ecosystem, and redirect the hardware as workloads change. Custom ASICs give a large operator lower cost or better efficiency on a workload it understands well, but the owner must fund design, software, and deployment and accept that the chip is less useful outside its intended job. Chinese accelerators add a third objective—availability under policy constraint—even when their cost per unit of effective compute is worse.

The right comparison therefore depends on the buyer. A frontier laboratory values programmability, training scale, and time to solution. A hyperscaler serving billions of repetitive inference requests may accept a narrower chip in exchange for lower operating cost. A Chinese operator may prefer a domestically available system that can actually be delivered over a theoretically superior imported part that cannot. “Best accelerator” has no meaning without the workload, system boundary, and procurement constraint.

Nvidia's moat is a synchronized release calendar

Nvidia has moved to a one-year architecture cadence. Its Vera Rubin NVL72 rack, ramping into production in 2026, combines 72 Rubin GPUs and 36 Vera CPUs and delivers 3.6 exaFLOPS of NVFP4 inference with 20.7 TB of HBM4 across the rack. Nvidia had not published a rack-power specification at the cutoff, so third-party estimates—including discussion near 600 kW for Rubin Ultra—remain estimates rather than product facts. A GB200 or GB300 NVL72 rack is estimated around $3M and a Vera Rubin rack at $5–7M, compared with $30–40k for a bare GPU. §2.13 examines the physical BOM, evidence grades, and normalized 100 MW implications.¹²

The cadence is itself the moat. Shipping a materially better rack every twelve months, co-designed across compute, networking, and cooling, raises the switching cost for any customer and strains every rival to keep pace. The risk is the mirror image: a one-year cadence stresses the entire supply chain beneath it, from the advanced packaging in Chapter 2.7 to the power in Chapter 2.3, and any slip would ripple outward. Reports of a possible Rubin Ultra "Kyber" delay circulated and were denied in 2026, the kind of rumor that will recur precisely because the cadence leaves no slack.

AMD is a second source; Intel is longer-dated manufacturing optionality

The merchant-GPU challenge to Nvidia is real but narrow. AMD is the credible number two, with its MI400 family on TSMC's 2nm process and its double-wide Helios rack, due in the third quarter of 2026, giving it a genuine rack-scale product for the first time; AMD claims the MI455X delivers many times the token throughput of its predecessor. The demand base finally arrived with the OpenAI agreement to deploy 6 GW of AMD chips, sweetened with warrants for up to 160M AMD shares, plus a multi-gigawatt Meta commitment. AMD's data-center revenue reached $5.8B in the first quarter of 2026, up 57%, though its share of AI accelerators remains in the mid-single digits.

Intel is the also-ran of this layer. Its Gaudi line missed even a modest $500M target, and its go-forward story is Crescent Island, an inference GPU in customer testing in the second half of 2026, and Jaguar Shores, a 2027 rack-scale design built around silicon photonics. Intel's relevance in accelerators is now a 2027 question, and the roughly 10% US government equity stake in it (Chapter 2.8) is a bet on its foundry, not its GPUs.

Custom ASICs absorb stable workloads and reward their enablers

The most important competitive shift in this layer is that the hyperscalers are increasingly designing their own chips. Custom application-specific chips (ASICs) are growing at roughly a 45% annual rate against about 16% for merchant GPUs. Google's TPU is the most mature, now on its seventh generation ("Ironwood"); Amazon has deployed over 500,000 Trainium chips, the largest ASIC fleet by unit count; Microsoft has Maia and Meta has MTIA; and OpenAI signed a 10 GW custom-silicon program with Broadcom in October 2025, first volume expected in 2027.

None of the hyperscalers designs these chips alone. Broadcom and Marvell are important enablers of custom silicon and can participate across several customer programs. That diversification reduces dependence on a single accelerator architecture but does not eliminate customer concentration, program timing or valuation risk. Industry forecasts that ASIC unit shipments overtake merchant GPUs should be treated as scenario inputs rather than a guarantee that design-service economics accrue equally to both suppliers.³

Units, revenue, and compute tell different market-share stories

The competitive map only makes sense once you separate the scoreboards, because unit share is not revenue share and neither is compute share. By units, ASICs are about to lead. By revenue and profit, Nvidia dominates, with J.P. Morgan estimating about 75% of data-center accelerator revenue in 2026, protected by the CUDA software ecosystem of Chapter 2.4. By computing power at the frontier, Nvidia is more dominant still, because the custom chips mostly serve captive internal inference rather than frontier training.

Forecasts for Nvidia's inference share range from above 90% today to 20–30% by 2028, while Morgan Stanley argues that custom silicon does not threaten Nvidia's overall dominance. A middle case is that ASICs absorb lower-margin internal inference while Nvidia retains frontier training, the merchant market, and software-linked system economics. Under that outcome, an ASIC crossover in unit count would not imply a crossover in revenue. Cloud deployments, rental prices, and merchant-system sales will distinguish among these cases.

China is using system scale to compensate for weaker components

The United States leads frontier AI compute and its software through Nvidia, AMD, and Broadcom. Export controls and domestic procurement rules are pushing China to build a parallel supply chain. Huawei's Ascend line leads that effort, with roughly 600,000 Ascend 910C accelerators planned for 2026 and a roadmap that includes in-house high-bandwidth memory. Cambricon (寒武纪, 688256.SH) is the listed pure-play and is tripling output toward roughly 500,000 accelerators; Biren, MetaX, Moore Threads, and Hygon (海光, 688041.SH) follow. Nvidia's share of China's AI-chip market has fallen from about 95% in 2022 to effectively zero in covered data-center procurement, driven primarily by policy and access rather than an open performance comparison.

The gap is real and worth stating precisely. Chinese accelerators trail on a per-chip basis, and Huawei's claim that an Ascend cluster beats Nvidia's is a system-level argument that uses several times as many chips and far more power to get there. Its software stack, Huawei's CANN, lags CUDA's fifteen-year head start badly. And the true ceilings on the Chinese ramp are not design but manufacturing: SMIC's yields and the domestic supply of high-bandwidth memory, both covered in later chapters. This is the layer where the bifurcation of Chapter 2.12 is most concrete, two separate compute ecosystems that no longer interoperate.

A roadmap becomes investable only when it becomes deliverable

The competitive outlook depends on three observable questions. Will custom ASICs expand beyond captive inference into external revenue? Relevant evidence includes Google offering TPU capacity outside its own workloads and OpenAI's Broadcom silicon shipping at volume in 2027. Can Nvidia maintain inference share as alternatives improve? Rental prices, cloud deployments, and merchant-system revenue matter more than unit forecasts alone. How quickly can Chinese supply grow? SMIC capacity, yield, and domestic memory remain the limiting inputs. All three also depend on Nvidia maintaining its annual release cadence without disrupting packaging, memory, and power planning.

A product announcement is only the first gate. The design must reach working silicon, meet its performance and power targets, qualify memory and packaging, enter complete systems, obtain production software support, and ship in enough volume to appear in customer workloads. Revenue can accrue at different points to design partners, foundries, memory vendors, system makers, and the chip company itself. Calling all of those stages “the next generation” hides several years of timing risk.

This matters most for comparison. Nvidia’s current rack should not be compared with a competitor’s roadmap peak specification as though both were available for purchase. A disclosed upper-bound configuration should not be normalized as a typical shipment. A supplier named in a prototype may not retain the socket in volume production. The evidence labels in §2.13 are not editorial caution; they are the difference between an investable order path and a technology aspiration.

Who can turn accelerator growth into shareholder returns

Nvidia (NVDA) remains the system integrator to beat, protected by CUDA, networking and an annual platform cadence; its risks include inference-share pressure, customer internalization and policy exposure. Broadcom (AVGO) and Marvell (MRVL) provide custom-silicon exposure across hyperscaler programs while adding networking and optics exposure; program concentration and valuation differ materially between them. AMD (AMD) is a merchant second source with real rack-scale demand but a smaller installed software base; Intel's listed thesis increasingly depends on foundry execution. On the Chinese side, Cambricon and Hygon are listed expressions of mandated domestic demand, but access, policy and localization expectations can dominate near-term fundamentals.

What would falsify the thesis

The Nvidia thesis breaks if inference-share loss becomes real in the revenue line rather than the rumor mill, which a genuine, externally-adopted hyperscaler ASIC operating at training scale would signal. It also breaks, from the other direction, if a second efficiency shock in the models layer cuts the compute intensity of inference faster than volume grows, or if the one-year cadence slips and the supply chain seizes. The Chinese thesis changes if SMIC and domestic high-bandwidth memory break their current ceilings, letting Ascend and Cambricon ship at true frontier scale, which would turn a mandated, subsidized market into a competitive one and pressure the American incumbents in the third-country markets that Chapter 2.12 calls the real prize.

The practical conclusion is to follow the customer’s purchasing equation instead of arguing about a permanent chip champion. For training, watch time to solution, software reliability, and the ability to scale a large cluster. For inference, watch cost per completed token or task, power, latency, and how easily software can move. For every platform, watch whether the surrounding memory, network, cooling, and manufacturing supply can arrive on the same date.

Then translate that customer advantage into the security. Ask how much of the system’s selling price the company captures, what gross margin it keeps, how concentrated the buyers are, how much capital or share dilution supports the contract, and what level of future dominance the valuation already assumes. The chip can be essential and the stock can still disappoint. The investment works only when technical advantage becomes delivered systems, delivered systems become durable margin, and that margin exceeds the expectation embedded in the price.

Sources

Linked evidence for this chapter's figures and load-bearing claims: ^{3 1 2}